The present invention is directed to a method of assembling semiconductor device, and, more particularly, to semiconductor devices that have redistribution interconnections between internal contacts on one or more semiconductor dies and external contacts exposed on an active face of the device package.
Semiconductor device packaging fulfils basic functions such as providing electric connections and protecting the die against mechanical and environmental stresses. Continued progress in reduction of the size of the semiconductor dies and increased functionality and complexity of the electronic circuits integrated in the dies requires size reduction of the packaging with the same or greater complexity of the electrical connections with external circuits.
Semiconductor devices are commonly encapsulated for surface mounting by embedding one or more semiconductor dies in a mold compound. The external electrical contacts for connection with external circuits are exposed at the active face of the package and connected internally with electrical contact pads on the semiconductor die of smaller size and spacing. The exposed external contacts may be a ball grid array (BGA) or a land grid array (LGA), for example. Various techniques are available for connecting the exposed external electrical contacts of the package with the internal contacts of the embedded semiconductor die.
Minimum values are specified for the size of the individual exposed external electrical contact surfaces at the active face of the device and for the spacing between adjacent external electrical contact surfaces. Such specifications necessitate a compromise between the overall size of the active face of the device and the number of individual external electrical contact surfaces.
In wafer level packaging (WLP), the redistribution layer is built up on the wafer before the devices are separated by singulation and then the devices are encapsulated. The exposed external contacts are limited to the area of the active face of the die, the redistribution layer serving to ‘fan in’ the contacts so as to make greater use of the available die face area, than if the exposed external contacts of the device were aligned with the positions of the internal contacts on the semiconductor die dictated by the topography of the underlying circuits in the body of the semiconductor material.
In a technique known as redistributed chip packaging (RCP), after singulation of the semiconductor die a redistribution layer provides electrical interconnections between the internal set of contacts on the semiconductor die and the exposed external contacts at the active face of the device, to route out signal connections and power and ground connections. The redistribution layer fans out the exposed external contacts, offering a larger area than the active face of the die for the exposed external contacts and enabling larger exposed contacts to be used, with greater spacing between them.
In one convenient technique of production of embedded RCP devices, an array of singulated dies is placed with their active faces on a temporary support. The dies are encapsulated by embedding the array with a molding compound and then releasing the encapsulated array from the support, forming an encapsulation layer of a panel. The encapsulation layer can then be processed by techniques somewhat similar to wafer processing to build up the redistribution layer on the active face of the panel. The redistribution layer may be built up from the active face of the panel by successive operations of depositing insulating material and depositing sets of electrical interconnections, which may have horizontal traces and vias providing vertical connections between the levels of horizontal traces, and which are separated by the insulating material from each other and from unintended connection with conductive surfaces of the die. The interconnections may be deposited by vapor deposition and/or electroplating techniques, and patterned using photo mask and batch process lithography, among other techniques. Connection with signal input/output and power and ground pads on the active faces of the dies may be made during deposition of the interconnections. The packaged devices are singulated after completion of the redistribution layer.
Unless precautions are taken, the encapsulation layer is subject to degrees of warping which interfere with holding it in a tool to perform subsequent processing operations. It is possible to reduce deformation of the encapsulation layer by securing the encapsulation layer to a stiffening plate using an adhesive but suitable stiffening plates, of ceramic for example, are expensive and detaching the panel from the plate by dissolving the adhesive can lengthen processing times unacceptably and deteriorate other components of the finished package.